1. Field of the Invention
The present invention relates to a synchronous signal detection circuit for use in an information recording apparatus or an information transmitting apparatus and capable of detecting a synchronizing code pattern, for example called "RESYNC" inserted into a reproduced signal and it also relates to an information reproducing apparatus having the same.
Although a description is made about an optical disk drive apparatus in this specification, the present invention is not limited to the optical disk. The present invention is able to be used in a magnetic disk, a disk using another recording medium, an information reproducing apparatus such as a tape and a card or a signal receiving portion of an information transmitting apparatus.
2. Description of the Related Arts
An example of a sector format of a reloadable type or rewriting type optical disk is shown in FIG. 17. A plurality of RESYNC are inserted into data in a data portion in such a manner that one byte of RESYNC is inserted at predetermined intervals, for example, one byte of the same is inserted with respect to 15 or 20 bytes of data. In a case wherein data is modulated in accordance with the (2, 7) code recording method, the RESYNC pattern hardly appears on the data pattern as "0010 0000 0010 0100" in accordance with the (2, 7) code rule. Then, a pattern which hardly encounters the erroneous detection is selected. A further detailed format of each of DATA, CONTROL, ECC, CRC and RESYNC is shown in FIG. 18. As shown in FIG. 18, SYNC and ensuing RESYNC are inserted at the same intervals. Referring to FIG. 18, symbol "SB" denotes SYNC and "RS" denotes RESYNC.
RESYNC is detected by a pattern matching circuit which is, as shown in FIG. 19, composed of a shift register 121 and AND gates 122 to 124. In the circuit shown in FIG. 19, a RESYNC detection signal is "1" at the moment at which an operation of inputting pattern "100000001001" has been completed. Although the RESYNC pattern is usually selected in such a manner that it does not appear in a DATA pattern, the major portion of the structures is arranged in such a manner that a window is established so that only the RESYNC detection signal detected in the window is recognized in order to prevent an erroneous detection of RESYNC due to deterioration in the quality of the reproduced signal.
FIG. 20 is a block diagram which illustrates an example of a RESYNC detection circuit and FIG. 21 illustrates a time chart about the operation performed by the circuit shown in FIG. 20. Although the third pulse of detected signals shown in FIG. 21 is generated due to an erroneous detection of RESYNC, the transmission of the above-described pulse can be prevented by the effect of the window. A window generating circuit 133 shown in FIG. 20 is a circuit arranged in such a manner that clocks are counted while making the SYNC signal be the reference so that a window is generated which is opened in the vicinity of a region in which the RESYNC detection signal transmitted from a RESYNC pattern matching circuit 131 is expected to be generated. The window must have a proper size to act as desired. The clock employed in FIGS. 19 and 20 is a clock which is generated by a PLL circuit and which is in synchronization with the reproduced signal.
FIG. 22 is a block diagram which illustrates a circuit for use in an ordinary information reproducing apparatus. Then, the schematic operation will now be described. Data recorded on a recording medium 150 is, as an analog signal, detected by a detector 151 before it is binarized by a binary circuit 152. Then, a sector mark detector 153 detects a sector mark (denoted by symbol "SM" shown in FIG. 17) from the above-described binary signal. A read gate generator 154 then opens the gate through which data is read. The PLL circuit is disposed in a data synchronizer 155 so as to transmit a synchronous clock 155a and synchronous data 155b which is made to be in synchronization with the synchronous clock 155a. The above-described clock 155a and the synchronous data 155b are supplied to a decoder 156 for transmitting decoded data, an address mark (denoted by symbol "AM" shown in FIG. 17) detector 157 for detecting an address mark and a SYNC/RESYNC detector 159 for detecting SYNC and RESYNC. The output from the address mark detector 157 is received by a read clock generator disposed in a preformat portion so that a clock for reading the preformat portion shown in FIG. 17 is generated. On the other hand, an output signal transmitted from the SYNC/RESYNC detector 159 is received by a read clock generator 160 disposed in the data portion so that a clock for reading the data portion shown in FIG. 17 is generated. An output shown in FIG. 22 is, as shown in a time chart shown in FIG. 23, transmitted while being formed into decoded data and a read clock which is in synchronization with the decoded data.
RESYNC acts to re-confirm the position of data if the phase of the clock is undesirably delayed or the frequency of the same is deviated due to lack of the reproducing signal or the deterioration in the quality of the signal. Therefore, if the RESYNC detection window is too narrow, RESYNC deviates from the window when the clock supplied from PLL is disordered. As a result, reading from that position cannot be performed. On the contrary, if the window is too wide, false RESYNC generated on the data due to an error is erroneously detected. As a result, ensuing reading also cannot be performed.